1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more specifically, to a synchronous semiconductor memory device taking in an external signal in synchronization with a clock signal applied periodically from outside.
2. Description of the Background Art
Generally, in a synchronous semiconductor memory device, data is externally input and thereafter the data is written to a memory cell array. In order to allow writing at high fiequency, data is written several bits by several bits (for example, 2 bits by 2 bits). In this manner, the time in which writing to the memory cell array is possible can be improved to about twice the operation frequency.
The collective writing operation, however, prevents writing to the memory cell array immediately after the input of the data, and the data can be written to the memory array only after the several bits of data are input. An example in which 4 bits of data (d0, d1, d2, d3) are input will be described in the following. The data d0 input first is not immediately written to the memory cell array but after the input of the next data d1, d2 bits, that is, (d0, d1) are written to the memory cell array simultaneously.
By contrast, in reading operation, in order to make short the latency (the time period from an input of a command until data output), the data is read from the memory cell array immediately after the input of a read command.
Therefore, when a read command is input immediately after a write command, data collides in the memory cell array of the semiconductor memory (which is referred to as bus conflict), and hence such operation is inhibited by specification. A method effective in relaxing the restriction of the specification is late write.
In a general late write, when a write command is input, data input in response to a preceding write command is written to the memory cell array. This eliminates the necessity of waiting for the data input, and a write operation to the memory cell array can be initiated immediately after the input of the write command. As a result, writing to the memory cell array can be completed quickly and hence the subsequent reading operation can be performed more quickly than conventionally performed.
In the above described method, however, there is a problem at the time of a write command immediately after taking of a row address. The data written to the memory cell array at this time is the data input in response to a write command prior to the taking of the row address. If the row address to which the data is to be written is the same as the presently taken row address, there is no problem in writing. However, the row address may differ. In that case, writing is not possible.